Real-time lane detection and tracking on high performance computing devices

Road lane detection and tracking methods are the state of the art in present driver assistance systems. However, lane detection methods that exploit the parallel processing capabilities of heterogeneous high performance computing devices such as FPGAs (or GPUs), a technology that potentially will replace ECUs in a coming generation of cars, are a rare subject of interest. In this thesis a road lane detection and tracking algorithm is developed and implemented, especially designed to incorporate one or many, and even heterogeneous, hardware accelerators. Road lane markings are detected and tracked with a Sequential Monte Carlo (SQR) method. Lane detection is done by populating a pre-processed gradient image with randomly sampled, straight lines. Each line is assigned a weight according to its position and the best positioned lines are used to represent the lane markings. Subsequently, lane tracking is performed with the help of a particle filter. The code was tested on three devices, one GPU the NVIDIA GeForce GTX 660 TI and two FPGAs the ALTERA Stratix V and the ALTERA Cyclone V SOC. The tests revealed a processing frame rate of up to 627 Hz on the GPU, 478 Hz on the Stratix V FPGA and 38 Hz on the Cyclone V SOC. They also showed a significant improvement in accuracy and robustness, a 2.4-4.6 times faster execution on the GPU, a 8.4-29.7 times faster execution on the Stratix V and a reduction of memory consumption by 71.94 % compared to a similar lane detection method. The algorithm was tested on different recorded videos, on independent benchmark datasets and in multiple test drives, confronting it with a wide range of scenarios, such as varying lighting conditions, presence of disturbing shadows or light beams and varying traffic densities. In all these scenarios the algorithm proved to be very robust to detect and track one or multiple lane markings.